Seal ring formation is an important part in the back-end of semiconductor processes. Seal rings are stress protection structures around integrated circuits, protecting the internal circuit inside semiconductor chips from damage caused by the dicing of the semiconductor chips from wafers.
A typical seal ring is formed of interconnected metal lines and connecting vias. FIG. 1 is a schematic view of a part of seal ring 10. Seal ring 10 is typically formed on an inner side of dicing line 12, sometimes also referred to as a scribe line. Typically, there is a circuit region (not shown) on the left-hand side of the drawing and a dicing region (a region to be cut during dicing) on the right-hand side of the drawing.
Seal ring 10 includes interconnected metal components, which are formed of metal lines 14 and conductive vias 18, both formed in dielectric layers 16. Metal lines 14 and vias 18 are physically connected. Moreover, a passivation film 20 is formed over a top layer of seal ring 10.
Because of the provision of seal ring 10 and passivation film 20, the circuit region on the inner side of seal ring 10 is protected from influences of external environments, thus it is possible to ensure stability of properties of the semiconductor device over a long period of time. Typically, seal rings are electrically floating and do not provide electrical protection.
A further function of seal ring 10 is to protect the integrated circuits on the inner side of seal ring from moisture-induced degradation. Since dielectric layers 16 are typically formed of porous low-k dielectric materials, moisture can easily penetrate through low-k dielectric layer 16 to reach the integrated circuits. Since seal ring 10, which is formed of metal, blocks the moisture penetration path, the moisture penetration is significantly reduced.
To accommodate the ever-evolving requirement of customized applications, the design of seal rings needs to be customized. A customized design of the seal rings is introduced in the present invention.